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general description the max1422 3.3v, 12-bit analog-to-digital converter (adc) features a fully differential input, pipelined, 12- stage adc architecture with wideband track-and-hold (t/h) and digital error correction incorporating a fully-dif- ferential signal path. the max1422 is optimized for low- power, high dynamic performance applications in imaging and digital communications. the converter operates from a single 3.3v supply, consuming only 137mw while delivering a 67db (typ) signal-to-noise ratio (snr) at a 5mhz input frequency and a 20msps sampling frequency. the fully-differential input stage has a small signal -3db bandwidth of 400mhz and may be operated with single-ended inputs. an internal 2.048v precision bandgap reference sets the adcs full-scale range. a flexible reference structure accommodates an internally or externally applied buffered or unbuffered reference for applications requiring increased accuracy or a different input volt- age range. in addition to low operating power, the max1422 features two power-down modes, a reference power-down, and a shutdown mode. in reference power-down, the internal bandgap reference is deactivated, resulting in a 2ma (typ) supply current reduction. for idle periods, a full shutdown mode is available to maximize power savings. the max1422 provides parallel, offset binary, cmos- compatible three-state outputs. the max1422 is available in a 7mm ? 7mm ? 1.4mm, 48-pin tqfp package and is specified over the com- mercial (0? to +70?) and extended industrial (-40? to +85?) temperature ranges. pin-compatible higher-speed versions of the max1422 are also available. please refer to the max1421 data sheet for 40msps and the max1420 data sheet for 60msps. ________________________applications medical ultrasound imaging ccd pixel processing data acquisition radar if and baseband digitization features ? single 3.3v power supply ? 67db snr at f in = 5mhz ? internal 2.048v precision bandgap reference ? differential wideband input t/h amplifier ? power-down modes 130mw (reference shutdown mode) 10w (shutdown mode) ? space-saving 48-pin tqfp package max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference ________________________________________________________________ maxim integrated products 1 d9 d8 d7 d6 dv dd dv dd dgnd dgnd d5 d4 d3 d2 agnd av dd av dd agnd agnd inp inn agnd agnd av dd av dd agnd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 tqfp max1422 agnd av dd av dd agnd clk clk agnd av dd dv dd dgnd d0 d1 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 agnd av dd cml refn refp refin av dd agnd pd oe d11 d10 pin configuration 19-1899; rev 1; 5/04 ordering information part temp range pin-package MAX1422CCM 0? to +70? 48 tqfp max1422ecm -40? to +85? 48 tqfp functional diagram appears at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input voltage at -0.5dbfs, internal reference, f clk = 20mhz (50% duty cycle); digital output load c l = 10pf, +25? guaranteed by production test, <+25? guaranteed by design and characterization. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , dv dd to agnd ..............................................-0.3v to +4v dv dd , av dd to dgnd..............................................-0.3v to +4v dgnd to agnd.....................................................-0.3v to +0.3v inp, inn, refp, refn, refin, cml,clk, clk , ....................(agnd - 0.3v) to (av dd + 0.3v) d0?11, oe , pd .......................(dgnd - 0.3v) to (dv dd + 0.3v) continuous power dissipation (t a = +70?) 48-pin tqfp (derate 21.7mw/? above +70?)........1739mw operating temperature ranges MAX1422CCM ....................................................0? to +70? max1422ecm .................................................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution res 12 bits t a = +25?, no missing codes -1 1 differential nonlinearity dnl t a = t min to t max ?.5 lsb integral nonlinearity inl t a = t min to t max ? lsb mid-scale offset mso -3 ?75 3 %fsr mid-scale offset temperature coefficient msotc 3 ? 10 - 4 %/ c internal reference (note 1) -5 ?.1 5 external reference applied to refin, (note 2) -5 ?.2 5 gain error ge external reference applied to refp, cml, and refn (note 3) -1.5 1.5 %fsr gain error temperature coefficient getc external reference applied to refp, cml, and refn (note 3) 15 ? 10 - 6 %/ c dynamic performance (f clk = 20mhz, 4096-point fft) signal-to-noise ratio snr f in = 5mhz, t a = +25? 63 67 db spurious-free dynamic range sfdr f in = 5mhz, t a = +25? 64 74 dbc total harmonic distortion thd f in = 5mhz, t a = +25? -72 -63 dbc signal-to-noise and distortion sinad f in = 5mhz, t a = +25? 60 65 db effective number of bits enob f in = 5mhz 10.5 bits two-tone intermodulation distortion imd f in1 = 7.028mhz, f in2 = 8.093mhz (note 4) -77 dbc differential gain dg 1% differential phase dp 0.25 degrees analog inputs (inp, inn, cml) input resistance r in either input to ground 61 k ? input capacitance c in either input to ground 4 pf common-mode input level (note 5) v cml v av dd ? 0.5 v
max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units common-mode input voltage range (note 5) v cmvr v cml 5% v differential input range v in v inp - v inn (note 6) v diff v small-signal bandwidth bw -3db (note 7) 400 mhz large-signal bandwidth fpbw -3db (note 7) 150 mhz overvoltage recovery ovr 1.5 ? fs input 1 clock cycles internal reference (refin bypassed with 0.22? in parallel with 1nf) common-mode reference voltage v cml at cml v avdd ? 0.5 v positive reference voltage v refp at refp v cml + 0.512 v negative reference voltage v refn at refn v cml - 0.512 v differential reference voltage v diff (note 6) 1.024 5% v differential reference temperature coefficient reftc 100 ppm/ c external reference (v refin = 2.048v) refin input resistance r in (note 8) 5 k ? refin input capacitance c in 10 pf refin reference input voltage range v refin 2.048 10% v differential reference voltage range v diff (note 6) 0.92 ? ? external reference (v refin = 0, reference voltage applied to refp, refn, and cml) refp, refn, cml input current i in -200 200 ? refp, refn, cml input capacitance c in 15 pf differential reference voltage range v diff (note 6) 1.024 10% v cml input voltage range v cml 1.65 10% v refp input voltage range v refp v cml + v diff /2 v refn input voltage range v refn v cml - v diff /2 v digital inputs (clk, clk , pd, oe ) input logic high v ih 0.7 ? v dvdd v input logic low v il 0.3 ? v dvd v electrical characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input voltage at -0.5dbfs, internal reference, f clk = 20mhz (50% duty cycle); digital output load c l = 10pf, +25? guaranteed by production test, <+25? guaranteed by design and characterization. typical values are at t a = +25?.)
max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units clk, clk 330 pd -20 20 input current oe -20 20 ? input capacitance 10 pf digital outputs (d0?11) output logic high v oh i oh = 200? v d v dd - 0.5 v dvdd v output logic low v ol i ol = -200? 0 0.5 v three-state leakage -10 10 ? three-state capacitance 2pf power requirements analog supply voltage v avdd 3.138 3.3 3.465 v digital supply voltage v dvdd 2.7 3.3 3.63 v analog supply current i avdd 39 46 ma analog supply current with internal reference in shutdown v refin = 0 37 44 ma analog shutdown current pd = dv dd 20 ? digital supply current i dvdd 3ma digital shutdown current pd = dv dd 20 ? power dissipation p diss analog power dissipation 137 152 mw power-supply rejection ratio psrr (note 9) 1 mv/v timing characteristics maximum clock frequency f clk figure 6 20 mhz clock high t ch figure 6, clock period 50ns 25 ns clock low t cl figure 6, clock period 50ns 25 ns pipeline delay (latency) figure 6 7 clock cycles aperture delay t ad figure 10 2 ns aperture jitter t aj figure 10 2 ps data output delay t od figure 6 5 10 14 ns bus enable time t be figure 5 5 ns bus disable time t bd figure 5 5 ns electrical characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input voltage at -0.5dbfs, internal reference, f clk = 20mhz (50% duty cycle); digital output load c l = 10pf, +25? guaranteed by production test, <+25? guaranteed by design and characterization. typical values are at t a = +25?.) note 1: internal reference, refin bypassed to agnd with a combination of 0.22? in parallel with 1nf capacitor. note 2: external 2.048v reference applied to refin. note 3: internal reference disabled. v refin = 0, v refp = 2.162v, v cml = 1.65v, and v refn = 1.138v. note 4: imd is measured with respect to either of the fundamental tones. note 5: specifies the common-mode range of the differential input signal supplied to the max1422. note 6: v diff = v refp - v refn. note 7: input bandwidth is measured at a 3db level. note 8: v refin is internally biased to 2.048v through a 10k ? resistor. note 9: measured as the ratio of the change in mid-scale offset voltage for a ?% change in v avdd , using the internal reference.
max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 5 -120 -60 -80 -100 -40 -20 0 04 3 12 5678910 fft plot (4096-point data record) max1422 toc01 analog input frequency (mhz) amplitude (db) hd2 hd3 f in = 5.2235mhz -120 -60 -80 -100 -40 -20 0 04 3 12 5678910 fft plot (4096-point data record) max1422 toc02 analog input frequency (mhz) amplitude (db) f in = 8.1637mhz hd2 hd3 -120 -60 -80 -100 -40 -20 0 04 3 12 5678910 fft plot (4096-point data record) max1422 toc03 analog input frequency (mhz) amplitude (db) f in = 19.8051mhz hd2 hd3 -120 -60 -80 -100 -40 -20 0 04 3 12 5678910 two-tone imd plot (4096-point data record) max1422 toc04 analog input frequency (mhz) amplitude (db) imd2 imd3 f in2 f in1 f in1 = 7.0283mhz f in2 = 8.0931mhz f clk = 20.0056mhz a in1 = a in2 = -6.5db fs 85 45 110100 spurious-free dynamic range vs. analog input frequency 53 max1422 toc05 analog input frequency (mhz) sfdr (dbc) 61 69 77 70 50 110100 signal-to-noise ratio vs. analog input frequency 54 max1422 toc06 analog input frequency (mhz) snr (db) 58 62 66 -50 -80 110 100 total harmonic distortion vs. analog input frequency -74 max1422 toc07 analog input frequency (mhz) thd (dbc) -68 -62 -56 70 50 110100 signal-to-noise plus distortion vs. analog input frequency 54 max1422 toc08 analog input frequency (mhz) sinad (db) 58 62 66 20 40 30 60 50 70 80 -60 -40 -30 -50 -20 -10 0 spurious-free dynamic range vs. analog input power (f in = 5mhz) max1422 toc09 analog input power (db fs) sfdr (dbc) 10 0 t ypical operating characteristics (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input drive, a in = -0.5dbfs, f clk = 20mhz (50% duty cycle) digital output load c l = 10pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.)
max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference 6 _______________________________________________________________________________________ 0 20 40 60 80 100 -60 -40 -50 -30 -20 -10 0 signal-to-noise ratio vs. analog input power (f in = 5mhz) max1422 toc10 analog input power (db fs) snr (db) -80 -70 -30 -40 -20 -10 -60 -40 -50 -30 -20 -10 0 total harmonic distortion vs. analog input power (f in = 5mhz) max1422 toc11 analog input power (db fs) thd (dbc) -50 -60 0 60 50 70 80 -60 -40 -50 -30 -20 -10 0 signal-to-noise plus distortion vs. analog input power (f in = 5mhz) max1422 toc12 analog input power (db fs) sinad (db) 20 10 30 40 64 68 76 72 80 84 -40 10 -15 35 60 85 spurious-free dynamic range vs. temperature max1422 toc13 temperature ( c) sfdr (dbc) f in = 5.5224mhz 60 62 66 64 68 70 -40 10 -15 35 60 85 signal-to-noise ratio vs. temperature max1422 toc14 temperature ( c) snr (db) f in = 5.5224mhz -77 -75 -71 -73 -69 -67 -40 10 -15 35 60 85 total harmonic distortion vs. temperature max1422 toc15 temperature ( c) thd (dbc) f in = 5.5224mhz 60 62 66 64 68 70 -40 10 -15 35 60 85 signal-to-noise plus distortion vs. temperature max1422 toc16 temperature ( c) sinad (db) f in = 5.5224mhz 2 1 0 -1 -2 0 2048 1024 3072 4096 integral nonlinearity vs. digital output code max1422 toc17 digital output code inl (lsb) 0.50 0.25 0 -0.25 -0.50 02048 1024 3072 4096 differential nonlinearity vs. digital output code max1422 toc18 digital output code dnl (lsb) t ypical operating characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input drive, a in = -0.5dbfs, f clk = 20mhz (50% duty cycle) digital output load c l = 10pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.)
max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 7 0.5 0.2 -0.1 -0.4 -0.7 -40 10 -15 35 6 085 gain error vs. temperature, external reference (v refin = 2.048v) max1422 toc19 temperature ( c) gain error (%fsr) -1.0 50 46 42 38 34 -40 10 -15 35 6 085 analog supply current vs. temperature max1422 toc20 temperature ( c) i avdd (ma) 30 6 5 4 3 2 -40 10 -15 35 6 085 digital supply current vs. temperature max1422 toc21 temperature ( c) i dvdd (ma) c l = 10pf 1 0 50 60 55 70 65 75 80 5.0 10.0 12.5 7.5 15.0 17.5 20.0 snr/sinad, thd/sfdr vs. clock frequency max1422 toc22 clock frequency (mhz) snr/sinad, thd/sfdr (db, dbc) 45 40 f in = 5mhz sinad thd sfdr snr 2.05 2.04 2.03 2.02 2.01 3.1 3.3 3.2 3.4 internal reference voltage vs. analog supply voltage max1422 toc23 v dd (v) v refin (v) 3.5 2.00 2.00 2.02 2.06 2.04 2.08 2.10 -40 10 -15 35 60 85 internal reference voltage vs. temperature max1422 toc24 temperature ( c) v refin (v) 0 10,000 5000 20,000 15,000 25,000 30,000 n-1 n+2 output noise histogram (dc-input) max1422 toc25 digital output noise counts n-4 n-3 n n+1 n+3 27360 16623 3431 15029 162 22 1 2596 2 310 n-2 n+4 n+5 t ypical operating characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input drive, a in = -0.5dbfs, f clk = 20mhz (50% duty cycle) digital output load c l = 10pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.)
max1422 detailed description the max1422 uses a 12-stage, fully differential, pipelined architecture (figure 1), that allows for high- speed conversion while minimizing power consump- tion. each sample moves through a pipeline stage every half-clock cycle. including the delay through the output latch, the latency is seven clock cycles. a 2-bit (2-comparator) flash adc converts the held- input voltage into a digital code. the following digital- to-analog converter (dac) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. the resulting error signal is then multiplied by two and the product is passed along to the next pipeline stage. this process is repeated until the signal has been processed by all 12 stages. each stage provides a 1-bit resolution. digital error correction compensates for adc compara- tor offsets in each pipeline stage and ensures no missing codes. 12-bit, 20msps, 3.3v, low-power adc with internal reference 8 _______________________________________________________________________________________ pin description pin name function 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 agnd analog ground. connect all return paths for analog signals to agnd. 2, 3, 10, 11, 14, 15, 20, 42, 47 av dd analog supply voltage. for optimum performance, bypass to the closest agnd with a parallel combination of a 0.1?, and a 1nf capacitor. connect a single 10? and 1? capacitor combination between av dd and agnd. 6 inp positive analog signal input 7 inn negative analog signal input 17 clk clock frequency input. clock frequency input ranges from 100khz to 20mhz. 18 clk complementary clock frequency input. this input is used for differential clock input. if the adc is driven with a single-ended clock, bypass clk with 0.1? capacitor to agnd. 21, 31, 32 dv dd digital supply voltage. for optimum performance, bypass to the closest dgnd with a parallel combination of a 0.1? and a 1nf capacitor. connect a single 10? and 1? capacitor combination between dv dd and dgnd. 22, 29, 30 dgnd digital ground 23?8 d0?5 digital data outputs. data bits d0 through d5, where d0 represents the lsb. 33?8 d6?11 digital data outputs. d6 through d11, where d11 represents the msb. 39 oe output enable input. a logic "1" on oe places the outputs d0?11 into a high-impedance state. a logic "0" allows for the data bits to be read from the outputs. 40 pd shutdown input. a logic "1" on pd places the adc into shutdown mode. 43 refin external reference input. bypass to agnd with a capacitor combination of 0.22? in parallel with 1nf. refin can be biased externally to adjust reference levels and calibrate full-scale errors. to disable the internal reference, connect refin to agnd. 44 refp positive reference i/o. bypass to agnd with a capacitor combination of 0.22? in parallel with 1nf. with the internal reference disabled (refin = agnd), refp should be biased tov cml + v diff /2. 45 refn negative reference i/o. bypass to agnd with a capacitor combination of 0.22? in parallel with 1nf. with the internal reference disabled (refin = agnd), refn should be biased to v cml - v diff /2. 46 cml common-mode level input. bypass to agnd with a capacitor combination of 0.22? in parallel with 1nf. with the internal reference disabled (refin = agnd).
input track-and-hold transconductance circuit figure 2 displays a simplified functional diagram of the input track-and-hold (t/h) circuit in both track-and-hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuit samples the input signal onto the two capacitors (c2a and c2b) through-switches (s4a and s4b). switches s2a and s2b set the common mode for the transconduc- tance amplifier (ota) input and open simultaneously with s1, sampling the input waveform. the resulting differential voltage is held on capacitors c2a and c2b. switches s4a and s4b, are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier, and switch s4c is closed. the ota is used to charge capacitors, c1a and c1b, to the same values originally held on c2a and c2b. this value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. the wide input bandwidth, t/h amplifier allows the max1422 to track and sample/hold analog inputs of high frequencies beyond nyquist. the analog inputs inp and inn can be driven either differentially or single-ended. match the impedance of inp and inn and set the common-mode voltage to midsupply (av dd /2) for optimum perfor- mance. analog input and reference configuration the full-scale range of the max1422 is determined by the internally generated voltage difference between refp (av dd /2 + v refin /4) and refn (av dd /2 - v refin /4). the max1422? full-scale range is adjustable through refin, which provides a high input impedance for this purpose. refp, cml (av dd /2), and refn are internally buffered, low impedance outputs. the max1422 provides three modes of reference oper- ation: ? internal reference mode ? buffered external reference mode ? unbuffered external reference mode in internal reference mode, the on-chip 2.048v bandgap reference is active and refin, refp, cml, and refn, left floating. for stability purposes bypass refin, refp, refn, and cml with a capacitor network of 0.22?, in parallel with a 1nf capacitor to agnd. in buffered external reference mode, the reference volt- age levels can be adjusted externally by applying a stable and accurate voltage at refin. in unbuffered external reference mode, refin is con- nected to agnd, which deactivates the on-chip buffers of refp, cml, and refn. with their buffers shut down, max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 9 t/h v out x2 flash adc dac 2 bits mdac 12 v in v in stage 1 stage 2 d11?0 digital correction logic stage 12 to next stage figure 1. pipelined architecture s3b s3a cml s5b s2b s5a in+ in- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias ota internal bias cml s2a figure 2. internal t/h circuit
max1422 these nodes become high impedance and can be driven by external reference sources, as shown in figure 3. clock inputs (clk, clk ) the max1422? clk and clk inputs accept both sin- gle-ended and differential input operation, and accept cmos-compatible clock signals. if clk is driven with a single-ended clock signal, bypass clk with a 0.1? capacitor to agnd. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). in particu- lar, sampling occurs on the rising edge of the clock sig- nal, requiring this edge to have the lowest possible jitter. any significant aperture jitter would limit the snr performance of the adc according to the following relationship: where f in represents the analog input frequency, and t aj is the aperture jitter. clock jitter is especially critical for high input frequency applications. the clock input should always be consid- ered as an analog input and routed away from any ana- log or digital signal lines. the max1422 clock input operates with a voltage threshold set to av dd /2. clock inputs must meet the specifications for high and low periods, as stated in the electrical characteristics . figure 4 shows a simplified model of the clock input cir- cuit. this circuit consists of two 10k ? resistors to bias the common-mode level of each input. this circuit may be used to ac-couple the system clock signal to the max1422 clock input. output enable ( oe ), power-down (pd) and output data (d0?11) with oe high, the digital outputs enter a high-imped- ance state. if oe is held low with pd high, the outputs are latched at the last value prior to the power-down. all data outputs, d0 (lsb) through d11 (msb), are ttl/cmos logic compatible. there is a seven clock- cycle latency between any particular sample and its valid output data. the output coding is in offset binary format (table 1). the capacitive load on the digital outputs d0 through d11 should be kept as low as possible ( 10pf) to avoid large digital currents that could feed back into the ana- snr t db in aj = ? ? ? ? ? ? ? 20 1 2 10 log 12-bit, 20msps, 3.3v, low-power adc with internal reference 10 ______________________________________________________________________________________ max1422 refin refn r 50 ? r r r r 1v r 50 ? 50 ? r r av dd cml 0.1nf 0.22 f 0.1nf 0.22 f 0.1nf 0.22 f agnd av dd 4 max4284 max4284 refp av dd 2 av dd 4 av dd 2 figure 3. unbuffered external reference drive?nternal reference disabled
log portion of the max1421, thereby degrading its dynamic performance. the use of digital buffers (e.g. 74lvch16244) on the digital outputs of the adcs can further isolate the digital outputs from heavy capacitive loads. to further improve the max1422 dynamic perfor- mance, add small 100 ? series resistors to the digital output paths, close to the adc. figure 5 displays the timing relationship between output enable and data output. system timing requirements figure 6 depicts the relationship between the clock input, analog input, and data output. the max1422 samples the analog input signal on the rising edge of clk (falling edge of clk ). and output data is valid seven clock cycles (latency) later. figure 6 also dis- plays the relationship between the input clock parame- ters and the valid output data. applications information figure 7 depicts a typical application circuit containing a single-ended to differential converter. the internal ref- erence provides an av dd /2 output voltage for level- shifting purposes. the input is buffered and then split to a voltage follower and inverter. a lowpass filter at the input suppresses some of the wideband noise associ- ated with high-speed op amps. select the r iso and c in values to optimize the filter performance and to suit a particular application. for the application in figure 7, a r iso of 50 ? is placed before the capacitive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small bypassing capacitor.connecting c in from inn to inp may further improve dynamic perfor- mance. using transformer coupling an rf transformer (figure 8) provides an excellent solution to convert a single-ended signal to a fully dif- ferential signal, required by the max1422 for optimum performance. connecting the center tap of the trans- former to cml provides an av dd /2 dc level shift to the input. although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. in general, the max1422 provides better sfdr and thd with fully differential input signals over single- ended input signals, especially for very high input fre- quencies. in differential input mode, even-order harmonics are suppressed and each of the inputs requires only half the signal swing compared to single- ended mode. max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 11 d11?0 10k ? 10k ? 10k ? 10k ? a vdd adc clk clk inn inp agnd max1422 figure 4. simplified clock input circuit output data d11?0 oe t bd t be high-z high-z valid data figure 5. output enable timing differential input voltage* differential input offset binary v ref ? 2047/2048 +full scale - 1lsb 1111 1111 1111 v ref ? 2046/2048 +full scale - 2lsb 1111 1111 1110 v ref ? 1/2048 +1 lsb 1000 0000 0001 0 bipolar zero 1000 0000 0000 -v ref ? 1/2048 -1 lsb 0111 1111 1111 -v ref ? 2046/2048 -full scale +1 lsb 0000 0000 0001 -v ref ? 2047/2048 -full scale 0000 0000 0000 table 1. max1422 output code for differential inputs *v ref = v refp - v refn
max1422 single-ended, ac-coupled input signal figure 9 shows an ac-coupled, single-ended applica- tion, using a max4108 op amp. this configuration pro- vides high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal. grounding, bypassing and board layout the max1422 requires high-speed board layout design techniques. locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the adc, using surface-mount devices for minimum inductance. bypass refp, refn, refin, and cml with a parallel network of 0.22? capacitors and 1nf to agnd. av dd should be bypassed with a similar network of a 10? bipolar capacitor in parallel with two ceramic capacitors of 1nf and 0.1?. follow the same rules to bypass the digital supply dv dd to dgnd. multilayer boards with separate ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arrangement to match the physical location of the analog ground (agnd) and the digital output driver ground (dgnd) on the adcs package. the two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer dsp ground plane). route high-speed digital signal traces away from sensi- tive analog traces, and remove digital ground and power planes from underneath digital outputs. keep all signal lines short and free of 90 degree turns. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight-line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the max1422 are mea- sured using the best straight-line fit method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step-width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes. dynamic parameter definitions aperture jitter figure 10 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. 12-bit, 20msps, 3.3v, low-power adc with internal reference 12 ______________________________________________________________________________________ n - 7 n - 8 n n - 6 n + 1 n - 5 n + 2 n - 4 n + 3 n - 3 n + 4 n - 2 n + 5 n - 1 n n + 6 n + 7 7 clock-cycle latency analog input data output t do t ch t cl clk clk figure 6. system and output timing diagram
aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (figure 10). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical, minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adcs reso- lution (n-bits): snr (max) = (6.02 ? n + 1.76)db in reality, there are other noise sources besides quanti- zation noise e.g., thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spec- tral components minus the fundamental, the first four harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantization noise only. enob is computed from: enob sinad = - 176 602 . . max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 13 input 300 ? -5v 5v 0.1 f 0.1 f 0.1 f c in * 22pf c in * 22pf 1nf 0.22 f 44pf* r iso 50 ? r iso 50 ? -5v 600 ? 300 ? 300 ? inp inn lowpass filter cml 600 ? 5v -5v 0.1 f 300 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f 5v 0.1 f 300 ? max4108 max1422 max4108 max4108 lowpass filter *two c in (22pf) caps may be replaced by one 44pf cap, to improve performance. figure 7. typical application circuit for single-ended to differential conversion
max1422 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first four harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -6.5db full scale. thd vvvv v = +++ ? ? ? ? ? ? ? ? 20 10 2 2 3 2 4 2 5 2 1 log 12-bit, 20msps, 3.3v, low-power adc with internal reference 14 ______________________________________________________________________________________ max1422 1nf 1k ? 100 ? 100 ? c in 22pf cml c in 22pf inp inn 0.1 f r iso 50 ? r iso 50 ? 0.22 f v in max4108 figure 9. single-ended ac-coupled input max1422 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 1nf 0.1 f 0.22 f 25 ? 25 ? minicircuits t1?t?k81 inn inp cml 44pf * * * *replace both 22pf caps with 44pf between inp and inn to improve dynamic performance. figure 8. using a transformer for ac-coupling hold analog input sampled data (t/h) t/h t ad t aj track track clk clk figure 10. t/h aperature timing clk inp interface pipeline adc output drivers refin refp cml refn oe av dd agnd dv dd dgnd d11?0 inn pd t/h max1422 bandgap reference clk ref system + bias functional diagram
max1422 12-bit, 20msps, 3.3v, low-power adc with internal reference 32l/48l,tqfp.eps maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. pa c kag e information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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